I agree that sync generation or at least sync extraction is missing as DIY option for now.
Sync extraction, with manual setting of blanking, would be probably the easiest way, it requires to always have a video source but in this case, no need to rely on a digital solution.
Then for sync gen, composite sync is a bit complex to generate without using a micro/fpga, I’ve seen it done with a crystal and logic only, but this make for a big circuit, and only seen PAL or NTSC, I suppose allowing both with a same circuit would be a bit of a headache.
Though both rely on monostable for blanking.
While I was searching information about the subject, I found an article from Elektor magazine from 2005, which is a video sync generator made with a CPLD and written in verilog.
Video Sync Generator Elektor 07:08-2005.pdf
Basically, crystal clock is divided to get double the line frequency (31.25kHz in PAL), this divided clock increments a counter. Depending on the count, frequency and pulsewidth information is sent to a PWM that generate the pulse sequence.
I’ve started re-writing it for VHDL, took a bit of time as it was my first project, but recently managed to get the pulse sequence reset on Odd/Even.
With the pulse sequence resetting at each beginning of frame, the sync gen is locked vertically, though it still scroll horizontally. This should be solved by PLL+VCXO as it is done in Cadet Sync Gen, this way, the clock will be modulated until external horizontal sync and sync generator horizontal sync are in phase.
Haven’t tested the PLL part yet, as I didn’t not included it on the board I initially made.
So, far from being for sale in February 2021 I would say
Then, will be happy to share the code/implementation once I got something working