DIY video euro sync option in February 2021?

Occasionally I get people who want to start out in DIY eurorack video synthesis asking about my modules, and I have to let them know that right now their biggest challenge is finding a sync generator/extractor and an encoder.

Now Syntonie’s VU007 (LZX-compatible RGB to composite and component outputs) is about to solve the latter problem but I still don’t know of a currently-available DIY sync generator/extractor option. I built my own one (PAL sync extractor) on breadboard years ago, but it wasn’t particularly reliable, required fiddly manual calibration of the blanking circuit and I have no idea if it would work with NTSC or not.

So, putting the question out there - can anyone point me at a DIY sync generation or sync extractor option that’s currently available for sale, in February 2021?


I agree that sync generation or at least sync extraction is missing as DIY option for now.
Sync extraction, with manual setting of blanking, would be probably the easiest way, it requires to always have a video source but in this case, no need to rely on a digital solution.

Then for sync gen, composite sync is a bit complex to generate without using a micro/fpga, I’ve seen it done with a crystal and logic only, but this make for a big circuit, and only seen PAL or NTSC, I suppose allowing both with a same circuit would be a bit of a headache.



Though both rely on monostable for blanking.

While I was searching information about the subject, I found an article from Elektor magazine from 2005, which is a video sync generator made with a CPLD and written in verilog.

Video Sync Generator Elektor 07:08-2005.pdf (567.9 KB)

Basically, crystal clock is divided to get double the line frequency (31.25kHz in PAL), this divided clock increments a counter. Depending on the count, frequency and pulsewidth information is sent to a PWM that generate the pulse sequence.
I’ve started re-writing it for VHDL, took a bit of time as it was my first project, but recently managed to get the pulse sequence reset on Odd/Even.

With the pulse sequence resetting at each beginning of frame, the sync gen is locked vertically, though it still scroll horizontally. This should be solved by PLL+VCXO as it is done in Cadet Sync Gen, this way, the clock will be modulated until external horizontal sync and sync generator horizontal sync are in phase.

Haven’t tested the PLL part yet, as I didn’t not included it on the board I initially made.

So, far from being for sale in February 2021 I would say :sweat_smile:

Then, will be happy to share the code/implementation once I got something working :slight_smile:


Hang on… just filing this post under “Bastien is awesome” :slight_smile:


Probably not as much as the persons behind all the references I shared, but thanks :slight_smile:

Then, thinking about a short term solution, a sync extractor with monostable blanking is what would make the most sense, doesn’t require much circuitry (LM1881, 74HC4538, 74CH14, maybe a few op amps if 1V front sync/16 pin cable sync is required), most of the output of LM1881 can be buffered directly, except for blanking that needs to be derived from csync with monostable, then hsync could probably be subbed by csync without issue. Else, LMH1980 is worth considering, as it has hsync already, it is SMD but since LM1881 in DIP format is now obsolete, that can be a good option.

LM1881+4538+7414 is exactly the circuit I breadboarded, yes. I’ll go check it out and see if it’s suitable to make into a module…


I’m sunk under my audio/production workload so I can’t volunteer but using an ice40up5k (or an icebreaker dev board) with the open source tool chain seems like a much easier way to do this (as the elektor article suggests). It really is just logic/timers, this is what CPLDs and FPGAs are good for. CPLDs are pretty obsolete these days because low cost FPGAs are so cheap.
edit: re-read the thread, Bastien is on it, rad!!


Been using a Xilinx CoolrunnerII, got a CMOD C2 thinking it was a cheap devboard but its only a board with some pins, so definitely looking at other options, even more if it means more possibilities/being more easily accessible and tweakable with an open source toolchain.
Also, I’m quite close to max cells used in the XC2C64, my code is probably not super well optimized too, was hesitating in going with a bigger CPLD of the XC2 serie or using something different, so will definitely look into the ice40.

nice! I really like the open source toolchain and the ice40 (comes in friendly non-bga footprints too). I eventually moved up the to the ECP5 (more multipliers, more LUTs, faster fabric > 100MHz) but I sometimes think that was a mistake.
You have a bunch of choices in the ice40 family, I was using the ice40-up5k because I needed the DSP blocks.
I’m not sure I understand the “64 macrocell” topology of the coolrunner but the ice40s will get you 1k to 8k LUTs, plus BRAM, SPRAM, and DSP blocks (if you pick the UP5k) for only a dollar or two more depending on the device. Someone got DOOM to run on one recently :stuck_out_tongue:

The yosys toolchain is mostly verilog but they’ve added VHDL support in the past year or so, not sure how mature it is though.

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I’m not really familiar with the difference between LUTs and macrocells either. I think, in the case of macrocells, one cell = one flip-flop.
So for example, for a 10-bit counter as I uses for the pulse sequence, it takes 10 macrocells, it adds up quite fast so 64 is a bit small.

Then, if I understand correctly, another main difference is that the CPLD got a non-volatile memory, meaning it will start running the code once the CPLD is programmed and everytime the circuit is powered, while a FPGA needs some kind of microcontroller to load the code at each boot right?

oh yeah, that is very small. An LUT is also a register or flip flop.

The ICE40 series is very much a CPLD replacement. It also has the on board non-volatile memory (ECP5 does not), I have not used it though. It can also be programmed though SPI, if you include a small flash RAM connected to the boot port it knows to look there and program itself on power up. You can program the flash memory once with JTAG and it will automatically load from that each time (and you can reprogram the flash).

The dev boards generally include an FTDI chip that speaks USB and translates that to SPI for programming the flash or talking to the FPGA. You can also do this with a microcontroller but I haven’t tried yet. Definitely do not need a microcontroller with the FPGA.

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